1. Field of the Invention
The invention relates to the fabricating method of a flash memory, and more particular to the fabricating method of a flash memory which comprises a structure of a dynamic random access memory (DRAM).
2. Description of the Related Art
The development of nonvolatile devices has been intensively studied and progressed very quickly. Due to the inconvenience and low density, the conventional nonvolatile device is gradually substituted by a flash memory. The flash memory is therefore becomes more and more important.
Conventional flash memory arrays can be categorized into an NAND structure and an NOR structure, which are described as follows:
In 1990, a flash memory of Bi-polarity W/E NAND structure (of which the equivalent circuit is shown as FIG. 1A) was disclosed in a paper, "A NAND Structured Cell with a New Programming Technology for Highly Reliable 5V-only Flash EEPROM", by Toshiba. The paper is published in "VLSI Technology, pp. 129-130" by R. Kirisawa et al.
In 1992, a divided bit line NOR (DINOR) structure of a flash memory array (of which the equivalent circuit is shown as FIG. 1B) was disclosed in a paper, "A Novel Cell Structure Suitable for a 3V-Only Operation, Sector Era se Flash Memory", by Mitsubishi. The paper is published in "IEEE Tech. Dig. IEDM, pp.599-602", by H. Omoda et al.
In 1994, a NOR, AND structure of a flash memory array (of which the equivalent circuit is shown as FIG. 1C) was disclosed as the paper, "A 0.4-.mu.m.sup.2 Self-Aligned Contactless Memory Cell Technology Suitable for 256-Mbit flash memories" by Hitachi. The paper is published in "IEEE Tech. Dig. IEDM, pp.921-923", by M. Kato et al.
In 1995, a Dual String NOR (DuSNOR) structure of a flash memory array (of which the equivalent circuit is shown as FIG. 1D. It is similar to the disclosure presented by NEC in 1993) disclosed by Samsung. The paper, "A novel Dual String NOR Memory Cell Technology Scaleable to the 256Mbit and 1 Gbit Flash Memories" is published in "IEEE Tech. Dig. IEDM, pp.263-266", by K. S. Kim et al.
In 1995, an Asymmetrical Contactless Transistor (ACT) structure of a flash memory array (of which the equivalent circuit is shown as FIG. 1E) was disclosed by Hitachi. The paper, "A New Cell Structure for Sub-quarter Micron High Density Flash Memory", is published in "IEEE Tech. Dig. IEDM, pp.267-270", by Y. Yamauchi et al.
Referring to FIG. 2 and FIG. 1A to FIG. 1E, the common part of the above flash memory array structures can be represented by an equivalent circuit shown in FIG. 2. The conventional flash memory structure comprises a select transistor Q.sub.s2 and several memory cell transistors Q.sub.m2. The memory cell transistors Q.sub.m2 is connected to select transistors Q.sub.s2 via a local bit line (LBL) or a sub-bit line (SBL). A global bit lines GBL and the SBL are gated by the select transistor Q.sub.s2. Thus, only when the select transistor Q.sub.s2 is selected, the SBL can be connected to the GBL. Moreover, the memory cell transistors Q.sub.m2 are transistors with a floating gate which is, however, only a convenient way to describe a memory cell transistor. It does not mean that there is only one kind of memory cell transistor.
When the conventional flash memory is being coded or written, some select transistor Q.sub.s2 of the memory array must be in "on" status to write a signal into the memory cell transistors Q.sub.m2. Because the GBL voltage must be held until programming is completed, while writing a single memory cell, no signal can be written into any other memory cells sharing the same main bit line with this single memory cell before writing is completed. Namely, writing another signal of data into the main bit line has to wait until the previous coding is completed. Therefore, while coding or writing into a flash memory, there is only one coding process in act at a time in the memory cells which share the same main bit line. That is, there is only one signal allowed to write at a time. Thus, the operation speed of memory cells is limited and lowered.